Out-of-order microprocessors can provide improved computational performance by executing instructions in a sequence that is different from the order in the program, so that instructions are executed when their input data is available rather than waiting for the preceding instruction in the program to execute. In order to allow instructions to run out-of-order on a microprocessor it is useful to be able to rename registers used by the instructions. This enables the removal of “write-after-read” (WAR) dependencies from the instructions as these are not true dependencies. By using register renaming and removing these dependencies, more instructions can be executed out of program sequence, and performance is further improved. Register renaming is performed by maintaining a map of which registers named in the instructions (called architectural registers) are mapped onto the physical registers of the microprocessor. However, parallelism is still limited by true dependencies in the program, such as one instruction reading the result of the previous instruction.
A potential solution to this involves predicting the outcome of an instruction, such that future instructions can issue using the predicted value rather than waiting for the actual result. This breaks a true dependence, but if a prediction is incorrect, the effects of that prediction must be flushed or “rewound.”
The embodiments described below are not limited to implementations which solve any or all of the disadvantages of known methods of value prediction.